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1 features description applications ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 www.ti.com 14-bits, 125/105/80/65 msps adc with ddr lvds/cmos outputs radar systems maximum sample rate: 125 msps 14-bit resolution with no missing codes ads6145/ads6144/ads6143/ADS6142 (ads614x) 3.5 db coarse gain and up to 6 db are a family of 14-bit a/d converters with sampling programmable fine gain for snr/sfdr frequencies up to 125 msps. the high performance trade-off and low power consumption of the ads614x are parallel cmos and double data rate (ddr) combined in a compact 32 qfn package. an internal lvds output options high bandwidth sample and hold and a low jitter clock buffer help to achieve high snr and high sfdr even supports sine, lvcmos, lvpecl, lvds clock at high input frequencies. inputs, and clock amplitude down to 400 mv pp the ads614x feature coarse and fine gain options to improve sfdr performance at lower full-scale analog clock duty cycle stabilizer input ranges. internal reference with support for external reference the digital data outputs are either parallel cmos or ddr (double data rate) lvds. several features no external decoupling required for exist to ease data capture such as ? controls for references output clock position and output buffer drive strength, programmable output clock position and lvds current, and internal termination drive strength to ease data capture programmability. 3.3-v analog and 1.8-v to 3.3-v digital supply the output interface type, gain, and other functions 32-qfn package (5 mm 5 mm) are programmed using a 3-wire serial interface. alternatively, some functions are configured using pin compatible 12-bit family (ads612x) dedicated parallel pins so the device powers up to the desired state. the ads614x include internal references while wireless communications infrastructure eliminating traditional reference pins and associated software defined radio external decoupling. external reference mode is also power amplifier linearization supported. 802.16d/e the ads614x are specified over the industrial test and measurement instrumentation temperature range ( ? 40 c to 85 c). high definition video medical imaging ads614x performance summary ads6145 ads6144 ads6143 ADS6142 f in = 10 mhz (0 db gain) 90 91 93 95 sfdr, dbc f in = 170 mhz (3.5 db gain) 78 82 83 84 f in = 10 mhz (0 db gain) 73.7 74.1 74.5 74.6 sinad, dbfs f in = 170 mhz (3.5 db gain) 68.6 70.5 70.6 71.5 power, mw 417 374 318 285 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2007 ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ads61xx family 125 msps 105 msps 80 msps 65 msps ads614x ads6145 ads6144 ads6143 ADS6142 14 bits ads612x ads6125 ads6124 ads6123 ads6122 12 bits 2 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com sha 14-bit adc clock gen reference digital encoder and serializer control interface inp inm clkp clkm vcm clkoutpclkoutm d0_d1_p d0_d1_m d2_d3_p d4_d5_p d6_d7_p d8_d9_p d10_d11_p d12_d13_p d2_d3_md4_d5_m d6_d7_m d8_d9_m d10_d11_m d12_d13_m ads614x sclk sen sdata reset lvds mode avdd agnd drvdd drgnd pdn
absolute maximum ratings (1) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 package/ordering information (1) specified package- package package ordering product temperature transport media lead designator marking number range ads6145irhbt tape and reel, small ads6145 qfn-32 (2) rhb ? 40 c to 85 c az6145 ads6145irhbr tape and reel, large ads6144irhbt tape and reel, small ads6144 qfn-32 (2) rhb ? 40 c to 85 c az6144 ads6144irhbr tape and reel, large ads6143irhbt tape and reel, small ads6143 qfn-32 (2) rhb ? 40 c to 85 c az6143 ads6143irhbr tape and reel, large ADS6142irhbt tape and reel, small ADS6142 qfn-32 (2) rhb ? 40 c to 85 c az6142 ADS6142irhbr tape and reel, large (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) for thermal pad size on the package, see the mechanical drawings at the end of this data sheet. q ja = 34 c/w (0 lfm air flow), q jc = 30 c/w when used with 2 oz. copper trace and pad soldered directly to a jedec standard four layer 3 in 3 in (7.62 cm 7.62 cm) pcb. value unit supply voltage range, avdd ? 0.3 to 3.9 v v i supply voltage range, drvdd ? 0.3 to 3.9 v voltage between agnd and drgnd ? 0.3 to 0.3 v voltage between avdd to drvdd ? 0.3 to 3.3 v voltage applied to vcm pin (in external reference mode) ? 0.3 to 2 v voltage applied to analog input pins, inp and inm ? 0.3 to minimum ( 3.6, avdd + 0.3) v voltage applied to analog input pins, clkp and clkm ? 0.3 to (avdd + 0.3) v t a operating free-air temperature range ? 40 to 85 c t j operating junction temperature range 125 c t stg storage temperature range ? 65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 3 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
recommended operating conditions ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 over operating free-air temperature range (unless otherwise noted) min nom max unit supplies avdd analog supply voltage 3 3.3 3.6 v cmos interface 1.65 1.8 to 3.3 3.6 v drvdd output buffer supply voltage (1) lvds interface 3 3.3 3.6 v analog inputs differential input voltage range 2 v pp v ic input common-mode voltage 1.5 0.1 v voltage applied on vcm in external reference mode 1.45 1.5 1.55 v clock input ads6145 1 125 ads6144 1 105 input clock sample rate, f s msps ads6143 1 80 ADS6142 1 65 sine wave, ac-coupled 0.4 1.5 lvpecl, ac-coupled 0.8 input clock amplitude differential v pp (v clkp ? v clkm ) lvds, ac-coupled 0.35 lvcmos, ac-coupled 3.3 input clock duty cycle 35% 50% 65% digital outputs default for c load 5 pf and drvdd 2.2 v strength maximum output buffer drive strength (2) for c load > 5 pf and drvdd 2.2 v strength maximum for drvdd < 2.2 v strength cmos interface, maximum buffer strength 10 maximum external load capacitance from c load lvds interface, without internal termination 5 pf each output pin to drgnd lvds interface, with internal termination 10 r load differential load resistance (external) between the lvds output pairs 100 ? t a operating free-air temperature -40 85 c (1) for easy migration to next generation, higher sampling speed devices (> 125 msps), use 1.8v drvdd supply. (2) see output buffer strength programmability in the application section. 4 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
electrical characteristics ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical values are at 25 c, min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, applies to cmos and lvds interfaces, unless otherwise noted. ads6145 ads6144 ads6143 ADS6142 f s = 125 msps f s = 105 msps f s = 80 msps f s = 65 msps parameter unit min typ max min typ max min typ max min typ max resolution 14 14 14 14 bits analog input differential input voltage range 2 2 2 2 v pp differential input resistance (dc), > 1 > 1 > 1 > 1 m ? see figure 94 differential input capacitance, 7 7 7 7 pf see figure 95 analog input bandwidth 450 450 450 450 mhz analog input common-mode current 180 151 114 92 m a (per input pin of each adc) reference voltages vrefb internal reference bottom voltage 1 1 1 1 v vreft internal reference top voltage 2 2 2 2 v v ref internal reference error -20 5 20 -20 5 20 -20 5 20 -20 5 20 mv (vreft ? vrefb) v cm common-mode output voltage 1.5 1.5 1.5 1.5 v v cm output current capability 4 4 4 4 ma dc accuracy no missing codes specified specified specified specified e o offset error -10 2 10 -10 2 10 -10 2 10 -10 2 10 mv offset error temperature coefficient 0.05 0.05 0.05 0.05 mv/ c there are two sources of gain error ? internal reference inaccuracy and channel gain error e gref gain error due to internal reference -1 0.25 1 -1 0.25 1 -1 0.25 1 -1 0.25 1 % fs inaccuracy alone, ( v ref /2) % e gchan gain error of channel alone (1) -1 0.3 1 -1 0.3 1 -1 0.3 1 -1 0.3 1 % fs channel gain error temperature 0.005 0.005 0.005 0.005 %/ c coefficient dnl differential nonlinearity -0.95 0.6 2 -0.95 0.6 2 -0.95 0.5 2 -0.95 0.5 2 lsb inl integral nonlinearity -4.5 2.5 4.5 -4.5 2.5 4.5 -4 2 4 -4 2 4 lsb power supply i avdd analog supply current 123 110 94 84 ma digital supply current, cmos interface, i drvdd 6.1 5.4 4.5 4.0 ma drvdd = 1.8 v, no load capacitance, f in = 2 mhz (2) digital supply current, lvds interface, i drvdd 42 42 42 42 ma drvdd = 3.3 v, with 100- ? external termination total power, cmos, 417 625 374 525 318 440 285 400 mw drvdd = 3.3 v (3) global power down 30 60 30 60 30 60 30 60 mw (1) specified by design and characterization; not tested in production. (2) in cmos mode, the drvdd current scales with the sampling frequency and the load capacitance on the output pins (see figure 87 ). (3) the maximum drvdd current depends on the actual load capacitance on the digital output lines. note that the maximum recommended load capacitance is 10 pf. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 5 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
electrical characteristics ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical values are at 25 c, min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, applies to cmos and lvds interfaces, unless otherwise noted. ads6145 ads6144 ads6143 ADS6142 f s = 125 msps f s = 105 msps f s = 80 msps f s = 65 msps parameter test conditions unit min typ max min typ max min typ max min typ max dynamic ac characteristics f in = 10 mhz 73.9 74.3 74.6 74.7 f in = 50 mhz 70 73.7 73.7 71 74.2 74.4 f in = 70 mhz 73.3 70 73.9 74.1 71 74.4 snr 0 db gain 71.1 71.8 72.3 72.7 signal-to-noise dbfs f in = 170 mhz 3.5 db coarse ratio, cmos 70.1 70.9 71.4 71.8 gain 0 db gain 69.8 70.7 71.3 71.7 f in = 230 mhz 3.5 db coarse 69 69.9 70.4 70.9 gain f in = 10 mhz 74.5 74.4 74.9 75 f in = 50 mhz 70.5 74.4 73.9 71.5 74.4 74.6 f in = 70 mhz 74.1 70.5 74.1 74.3 71.5 74.6 snr 0 db gain 72.3 72.3 72.8 72.9 signal-to-noise dbfs f in = 170 mhz 3.5 db coarse ratio, lvds 71.5 71.5 71.9 72.1 gain 0 db gain 71.2 71.2 71.8 72 f in = 230 mhz 3.5 db coarse 70.5 70.5 71.1 71.2 gain rms output inputs tied to common-mode 1.05 1.05 1.05 1.05 lsb noise f in = 10 mhz 73.7 74.1 74.5 74.6 f in = 50 mhz 69 72.3 73 70 74.1 74.1 f in = 70 mhz 72.6 69 73.2 73.3 70 74.0 sinad signal-to-noise 0 db gain 68.7 71 71.1 72.2 and distortion dbfs f in = 170 mhz 3.5 db coarse ratio 68.6 70.5 70.6 71.5 gain cmos 0 db gain 67.3 69 70.2 70.6 f in = 230 mhz 3.5 db coarse 67 69 69.9 70.4 gain f in = 10 mhz 74.3 74.3 74.8 74.9 f in = 50 mhz 69.5 72.7 72.9 70.5 74.3 74.4 f in = 70 mhz 73.4 69.5 73.5 73.6 70.5 74.4 sinad signal-to-noise 0 db gain 70.6 71.4 72 72.4 and distortion dbfs f in = 170 mhz 3.5 db coarse ratio 70.8 71.1 71.6 71.9 gain lvds 0 db gain 69.4 69.2 71 70.5 f in = 230 mhz 3.5 db coarse 69.4 69.4 70.7 70.5 gain enob f in = 50 mhz 11.1 11.7 11.3 12 effective bits f in = 70 mhz 11.1 11.8 11.3 12 number of bits f in = 10 mhz 90 91 93 95 f in = 50 mhz 76 80 83 79 89 89 f in = 70 mhz 84 78 84 84 79 86 sfdr 0 db gain 76 80 81 82 spurious free dbc f in = 170 mhz 3.5 db coarse dynamic range 78 82 83 84 gain 0 db gain 75 77 79 79 f in = 230 mhz 3.5 db coarse 76 79 81 82 gain 6 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 electrical characteristics (continued) typical values are at 25 c, min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, applies to cmos and lvds interfaces, unless otherwise noted. ads6145 ads6144 ads6143 ADS6142 f s = 125 msps f s = 105 msps f s = 80 msps f s = 65 msps parameter test conditions unit min typ max min typ max min typ max min typ max f in = 10 mhz 88.5 90 91.5 93 f in = 50 mhz 73 79.5 82.5 76 88 88 f in = 70 mhz 82 75 83 83 76 85 thd 0 db gain 73.5 79 78 80 total harmonic dbc f in = 170 mhz 3.5 db coarse distortion 75 81 79 82 gain 0 db gain 71.5 75.5 76 76 f in = 230 mhz 3.5 db coarse 72.5 77.5 78 78.5 gain f in = 10 mhz 96 96 97 98 f in = 50 mhz 76 95 96 79 96 96 f in = 70 mhz 91 78 92 93 79 93 hd2 0 db gain 81 83 83 86 second dbc f in = 170 mhz harmonic 3.5 db coarse 82 84 84 87 distortion gain 0 db gain 75 79 80 79 f in = 230 mhz 3.5 db coarse 76 81 81 81 gain f in = 10 mhz 90 91 93 95 f in = 50 mhz 76 80 83 79 89 89 f in = 70 mhz 84 78 84 84 79 86 hd3 0 db gain 76 80 81 82 third harmonic dbc f in = 170 mhz 3.5 db coarse distortion 78 82 83 84 gain 0 db gain 75 77 79 79 f in = 230 mhz 3.5 db coarse 76 79 81 82 gain f in = 10 mhz 93 94 96 97 f in = 50 mhz 92 90 93 96 worst spur (other than f in = 70 mhz 91 90 92 95 dbc hd2, hd3) f in = 170 mhz 90 89 89 91 f in = 230 mhz 90 88 89 90 imd 2-tone f1 = 185 mhz, f2 = 190 mhz, 83 82 84 88 dbfs intermodulation each tone at -7 dbfs distortion recovery to within 1% (of final input overload clock value) for 6-db overload with sine 1 1 1 1 recovery cycles wave input psrr ac power for 100 mvpp signal on avdd 35 35 35 35 dbc supply rejection supply ratio copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 7 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
digital characteristics (1) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1, avdd = 3.3 v ads6145/ads6144 parameter test conditions ads6143/ADS6142 min typ max unit digital inputs pdn, sclk, sdata, and sen (2) high-level input voltage 2.4 v low-level input voltage 0.8 v high-level input current 33 m a low-level input current ? 33 m a input capacitance 4 pf digital outputs cmos interface, drvdd = 1.8 to 3.3 v high-level output voltage drvdd v low-level output voltage 0 v output capacitance inside the device, from output capacitance 2 pf each output to ground digital outputs lvds interface, drvdd = 3.3 v, i o = 3.5 ma, r l = 100 ? (3) high-level output voltage 1375 mv low-level output voltage 1025 mv |v od | output differential voltage 225 350 mv v os output offset voltage, single-ended common-mode voltage of outp, outm 1200 mv output capacitance inside the device, from output capacitance 2 pf either output to ground (1) all lvds and cmos specifications are characterized, but not tested at production. (2) sclk and sen function as digital input pins when they are used for serial interface programming. when used as parallel control pins, analog voltage needs to be applied as per table 1 & table 2 (3) i o refers to the lvds buffer current setting, r l is the differential load resistance between the lvds output pair. 8 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
timing characteristics ? lvds and cmos modes (1) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical values are at 25 c, min and max values are across the full temperature range t min = ? 40 c to t max = 85 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp clock amplitude, c l = 5 pf (2) , i o = 3.5 ma, r l = 100 ? (3) , no internal termination, unless otherwise noted. for timings at lower sampling frequencies, see section output timings in the application information of this data sheet. ads6145 ads6144 ads6143 ADS6142 f s = 125 msps f s = 105 msps f s = 80 msps f s = 65 msps parameter test conditions unit min typ max min typ max min typ max min typ max aperture t a 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns delay aperture t j 150 150 150 150 fs rms jitter from global power 15 50 15 50 15 50 15 50 m s down wake-up time from standby 15 50 15 50 15 50 15 50 m s (to valid from output cmos 100 200 100 200 100 200 100 200 ns data) buffer lvds 200 500 200 500 200 500 200 500 ns disable clock latency 9 9 9 9 cycles ddr lvds mode (4) , drvdd = 3.3 v data valid (6) to data setup t su zero-cross of 1.7 2.3 2.5 3.1 3.9 4.5 5.4 6.0 ns time (5) clkoutp zero-cross of data hold t h clkoutp to data 0.7 1.7 0.7 1.7 0.7 1.7 0.7 1.7 ns time (5) becoming invalid (6) input clock rising edge clock zero-cross to output t pdi propagation 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 4.3 5.8 7.3 ns clock rising edge delay zero-cross duty cycle of lvds bit differential clock, clock duty (clkoutp- 40% 47% 55% 40% 47% 55% 40% 47% 55% 40% 47% 55% cycle clkoutm), 10 f s 125 msps rise time measured from ? 50 mv to 50 data rise mv, t r time, fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps t f data fall from 50 mv to ? 50 time mv, 1 f s 125 msps rise time measured from ? 50 mv to 50 t clkri output clock mv, se rise time, fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps t clkfa output clock from 50 mv to ? 50 ll fall time mv, 1 f s 125 msps parallel cmos mode, drvdd = 2.5 v to 3.3 v, default output buffer drive strength (7) data setup data valid (8) to 50% of t su 2.9 4.4 3.6 5.1 5.1 6.6 6.5 8.0 ns time (5) clkout rising edge 50% of clkout rising data hold t h edge to data becoming 1.3 2.7 2.1 3.5 3.6 5.0 5.1 6.5 ns time (5) invalid (8) (1) timing parameters are specified by design and characterization and not tested in production. (2) c l is the effective external single-ended load capacitance between each output pin and ground. (3) i o refers to the lvds buffer current setting; r l is the differential load resistance between the lvds output pair. (4) measurements are done with a transmission line of 100 ? characteristic impedance between the device and the load. (5) setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) data valid refers to a logic high of +100 mv and logic low of ? 100 mv. (7) for drvdd < 2.2 v, it is recommended to use an external clock for data capture and not the device output clock signal (clkout). see parallel cmos interface in the application section. (8) data valid refers to a logic high of 2 v (1.7 v) and logic low of 0.8 v (0.7 v) for drvdd = 3.3 v (2.5 v). copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 9 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 timing characteristics ? lvds and cmos modes (continued) for timings at lower sampling frequencies, see section output timings in the application information of this data sheet. ads6145 ads6144 ads6143 ADS6142 f s = 125 msps f s = 105 msps f s = 80 msps f s = 65 msps parameter test conditions unit min typ max min typ max min typ max min typ max clock input clock rising edge t pdi propagation zero-cross to 50% of 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 5 6.5 7.9 ns delay clkout rising edge duty cycle of output output clock clock (clkout), 45% 50% 55% 45% 50% 55% 45% 50% 55% 45% 50% 55% duty cycle 10 f s 125 msps rise time measured from 20% to 80% of data rise drvdd, t r time, fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns t f data fall from 80% to 20% of time drvdd, 1 f s 125 msps rise time measured from 20% to 80% of t clkri output clock drvdd, se rise time, fall time measured 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 0.8 1.5 2.4 ns t clkfa output clock from 80% to 20% of ll fall time drvdd, 1 f s 125 msps 10 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 1. latency figure 2. lvds mode timing figure 3. cmos mode timing copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 11 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com o o o o o o o o o o e e e e e e e e e e input clock clkoutm clkoutp output data dxp, dxm ddr lvds nC9 nC8 nC7 nC6 nC5 nC1 n n+1 n+2 nC9 nC8 nC7 nC6 nC5 n n+2 9 clock cycles 9 clock cycles clkout output data d0Cd13 parallel cmos input signal sample n n+1 n+2 n+3 n+4 t h t pdi t a t su t h t pdi clkp clkm n+9 n+10 n+11 n+12 t su e C even bits d0,d2,d4,d6,d8,d10,d12 o C odd bits d1,d3,d5,d7,d9,d11,d13 n+1 nC1 input clock output clock output data pair clkm clkoutp dn_dn+1_p, dn_dn+1_m clkp t pdi t su t h t h t su clkoutm (1) dn C bits d0, d2, d4, d6, d8, d10, d12 (2) dn+1 C bits d1, d3, d5, d7, d9, d11, d13 dn (1) dn+1 (2) input clock output clock output data clkm dn clkp t pdi t su t h clkout (1) dn C bits d0Cd13 dn (1)
device programming modes using serial interface programming only using parallel interface control only ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the ads614x have several features that can be easily configured using either parallel interface control or serial interface programming. to program using the serial interface, the internal registers must first be reset to their default values, and the reset pin must be kept low. in this mode, sen, sdata, and sclk function as serial interface pins and are used to access the internal registers of the adc. the registers are reset either by applying a pulse on the reset pin or by a high setting on the bit (d4 in register 0x00). the serial interface section describes register programming and register reset in more detail. to control the device using the parallel interface, keep reset tied high (avdd). now sen, sclk, sdata, and pdn function as parallel interface control pins. these pins can be used to directly control certain modes of the adc by connecting them to the correct voltage levels (as described in table 1 to table 3 ). there is no need to apply a reset pulse. frequently used functions are controlled in this mode ? standby, selection between lvds/cmos output format, internal/external reference, and 2s complement/straight binary output format. figure 4. simple scheme to configure parallel pins description of parallel pins table 1. sclk (analog control pin) sclk description 0 internal reference and 0 db gain (full-scale = 2 v pp ) (3/8) avdd external reference and 0 db gain (full-scale = 2 v pp ) (5/8) avdd external reference and 3.5 db coarse gain (full-scale = 1.34 v pp ) avdd internal reference and 3.5 db coarse gain (full-scale = 1.34 v pp ) table 2. sen (analog control pin) sen description 0 2s complement format and ddr lvds interface (3/8) avdd straight binary format and ddr lvds interface (5/8) avdd straight binary and parallel cmos interface avdd 2s complement format and parallel cmos interface 12 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com (3/8) avdd (3/8) avdd to parallel pin (sclk, sdata, sen) 3r avdd avdd gnd 3r2r (5/8) avdd (5/8) avdd gnd
serial interface register initialization ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 table 3. sdata, pdn (digital control pins) sdata pdn description low low normal operation low high (avdd) standby - only the adc is powered down high (avdd) low output buffers are powered down, fast wake-up time high (avdd) high (avdd) global power down. adc, internal reference, and output buffers are powered down, slow wake-up time the adc has a set of internal registers, which can be accessed through the serial interface formed by pins sen (serial interface enable), sclk (serial interface clock), sdata (serial interface data) and reset. after device power-up, the internal registers must be reset to their default values by applying a high-going pulse on reset (of width greater than 10 ns). serial shift of bits into the device is enabled when sen is low. serial data sdata is latched at every falling edge of sclk when sen is active (low). the serial data is loaded into the register at every 16th sclk falling edge when sen is low. if the word length exceeds a multiple of 16 bits, the excess bits are ignored. data is loaded in multiples of 16-bit words within a single active sen pulse. the first 5 bits form the register address and the remaining 11 bits form the register data. the interface can work with a sclk frequency from 20 mhz down to very low speeds (a few hertz) and also with a non-50% sclk duty cycle. figure 5. serial interface timing diagram after power-up, the internal registers must be reset to their default values. this is done in one of two ways: 1. either through a hardware reset by applying a high-going pulse on the reset pin (width greater than 10 ns) as shown in figure 5 . or 2. by applying a software reset. using the serial interface, set the bit (d4 in register 0x00) to high. this initializes the internal registers to their default values and then self-resets the bit to low. in this case the reset pin is kept low. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 13 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com sclk sen a 4 a3 a 2 a 1 a 0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register address register data sdata reset t sclk t dsu t dh t sloads t sloadh
serial interface timing reset timing ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical values at 25 c, min and max values across the full temperature range t min = ? 40 c to t max = 85 c, avdd = drvdd = 3.3 v (unless otherwise noted) min typ max unit f sclk sclk frequency = 1/t sclk > dc 20 mhz t sloads sen to sclk setup time 25 ns t sloadh sclk to sen hold time 25 ns t dsu sdata setup time 25 ns t dh sdata hold time 25 ns typical values at 25 c, min and max values across the full temperature range t min = ? 40 c to t max = 85 c, avdd = drvdd = 3.3 v (unless otherwise noted) parameter test conditions min typ max unit t 1 power-on delay delay from power-up of avdd and drvdd to reset pulse active 5 ms t 2 reset pulse width pulse width of active reset signal 10 ns t 3 register write delay delay from reset disable to sen active 25 ns t po power-up time delay from power-up of avdd and drvdd to output stable 6.5 ms note: a high-going pulse on the reset pin is required in serial interface mode in the case of initialization through a hardware reset. for parallel interface operation, reset has to be tied permanently high. figure 6. reset timing diagram 14 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com t 1 t 3 t 2 power supply avdd, drvdd reset sen
serial register map ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 table 4 gives a summary of all the modes that can be programmed through the serial interface. table 4. summary of functions supported by serial interface (1) (2) register address register functions in hex a4 - a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmos> clkout> output lvds or internal or output 00 gain> 0 0 software 0 0 adc power buffers cmos external clock buffer coarse gain reset down powered output reference powered down interface down edge> posn> 04 output data output output clock 0 0 0 0 0 0 0 0 position clock edge position control control control bit-wise or 09 byte-wise 0 0 0 0 0 0 0 0 0 0 control 2s 0a 0 0 0 0 0 0 0 complemen t or straight binary 0b 0 0 custom pattern lower 9 bits 0c 0 0 0 fine gain 0 to 6db custom pattern upper 5 bits 0e 0 double> lvds internal termination control for output data and clock lvds current control lvds current double 0f 0 0 0 0 0 0 0 cmos output buffer drive strength control (1) the unused bits in each register (shown by blank cells in above table) must be programmed as ? 0 ? . (2) multiple functions in a register can be programmed in a single write operation. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 15 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
description of serial registers ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 each register function is explained in detail. table 5. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 00 0 0 0 0 output buffers gain> lvds or cmos internal or software output clock adc power powered down coarse gain output interface external reset buffer powered down reference down d0 power down modes 0 normal operation 1 device enters standby mode where only adc is powered down. d2 power down modes 0 output clock is active (on clkout pin) 1 output clock buffer is powered down and becomes three-stated. data outputs are unaffected. d4 1 software reset applied - resets all internal registers and the bit self-clears to 0. d5 reference selection 0 internal reference enabled 1 external reference enabled d8 output interface selection 0 parallel cmos interface 1 ddr lvds interface d9 gain programming 0 0 db coarse gain 1 3.5 db coarse gain d10 power down modes 0 output data and clock buffers enabled 1 output data and clock buffers disabled 16 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 table 6. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 04 0 0 0 0 0 0 0 0 output data position output clock edge output clock control control position control d8 output clock position control 0 default output clock position after reset. the setup/hold timings for this clock position are specified in the timing specifications table. 1 output clock shifted (delayed) by 400 ps d9 0 use rising edge to capture data 1 use falling edge to capture data d10 0 default position (after reset) 1 data transition delayed by half clock cycle with respect to default position table 7. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 09 bit-wise or 0 0 0 0 0 0 0 0 0 0 byte-wise control d10 bit-wise or byte-wise selection (ddr lvds mode only) 0 bit-wise sequence - even data bits (d0, d2, d4,..d12) are output at the rising edge of clkoutp and odd data bits (d1, d3, d5,..d13) at the falling edge of clkoutp 1 byte-wise sequence - lower 7 data bits (d0-d7) are output at the rising edge of clkoutp and upper 7 data bits (d8-d13) at the falling edge of clkoutp copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 17 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 table 8. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 0a 0 0 0 0 0 0 0 2s complement or straight binary d7-d5 test patterns 000 normal operation - = adc output 001 all zeros - = 0x0000 010 all ones - = 0x3fff 011 toggle pattern - toggles between 0x2aaa and 0x1555 100 digital ramp - increments from 0x0000 to 0x3fff by one code every cycle 101 custom pattern - = contents of custom pattern registers 110 unused 111 unused d10 0 2s complement 1 straight binary table 9. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 0b 0 0 lower 9 bits of custom pattern table 10. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 0c 0 0 0 fine gain 0 to 6db upper 5 bits of custom pattern reg 0b - specifies lower 9 bits of custom pattern d10-d2 reg 0c - specifies upper 5 bits of custom pattern d4-d0 d10-d8 gain programming 000 0 db gain 001 1 db gain 010 2 db gain 011 3 db gain 100 4 db gain 101 5 db gain 110 6 db gain 111 unused 18 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 table 11. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 0e 0 double> lvds current lvds current control double d1-d0 lvds current programming d0 lvds data buffer current control 0 default current, set by 1 2x lvds current set by d1 lvds clock buffer current control 0 default current, set by 1 2x lvds current set by d3-d2 lvds current programming 00 3.5 ma 01 2.5 ma 10 4.5 ma 11 1.75 ma d9-d4 lvds internal termination d9-d7 internal termination for lvds output data bits 000 no internal termination 001 300 ? 010 185 ? 011 115 ? 100 150 ? 101 100 ? 110 80 ? 111 65 ? d6-d4 internal termination for lvds output clock 000 no internal termination 001 300 ? 010 185 ? 011 115 ? 100 150 ? 101 100 ? 110 80 ? 111 65 ? copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 19 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 table 12. a4 ? a0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (hex) 0f 0 0 0 0 0 0 0 cmos output buffer drive strength control d7-d4 output buffer drive strength controls 0101 weaker than default drive 0000 default drive strength 1111 stronger than default drive strength (recommended for load capacitances > 5 pf) 1010 maximum drive strength (recommended for load capacitances > 5 pf) other do not use combinations 20 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
pin configuration (cmos mode) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 rhb package (top view) figure 7. cmos mode pinout pin assignments ? cmos mode pin pin number pin name description type number of pins avdd analog power supply i 13, 15 2 agnd analog ground i 6, 9, 12 3 clkp, clkm differential clock inputs i 7, 8 2 inp, inm differential analog inputs i 10, 11 2 internal reference mode ? common-mode voltage output. vcm external reference mode ? reference input. the voltage forced on this pin sets the i/o 14 1 internal references. serial interface reset input. when using serial interface mode, the user must initialize the internal registers through a hardware reset by applying a high-going pulse on this pin, or by using reset the software reset option. see the serial interface section. i 2 1 in parallel interface mode, the user has to tie the reset pin permanently high. (sclk, sdata, and sen are used as parallel pin controls in this mode.) the pin has an internal 100-k ? pull-down resistor. this pin functions as the serial interface clock input when reset is low. when reset is tied high, it controls coarse gain and internal/external reference sclk selection. tie sclk low for internal reference and 0 db gain and high for internal i 3 1 reference and 3.5 db gain. see table 1 . the pin has an internal 100-k ? pull-down resistor. this pin functions as the serial interface data input when reset is low. it controls various power down modes along with the pdn pin when reset is tied high. sdata i 4 1 see table 3 for detailed information. the pin has an internal 100-k ? pull-down resistor. this pin functions as the serial interface enable input when reset is low. when reset is high, it controls output interface type and data formats. see table 2 for sen i 5 1 detailed information. the pin has an internal 100-k ? pull-up resistor to drvdd. pdn global power-down control pin i 16 1 copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 21 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com pdn drvdd agnd inp ovr inm clkout agnd a vdd avdd agnd clkp clkm 12 3 4 5 6 7 8 9 10 11 12 1314 15 16 d13 d12 d1 d11 d0 d10 d9 d8 reset d7 sclk d6 sdata d5 sen d4d3 d2 2423 22 21 20 19 18 17 31 30 2928 27 26 25 pad connected to drgnd 32 vcm
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 pin assignments ? cmos mode (continued) pin pin number pin name description type number of pins clkout cmos output clock o 26 1 d0 cmos output data d0 o 17 1 d1 cmos output data d1 o 18 1 d2 cmos output data d2 o 19 1 d3 cmos output data d3 o 20 1 d4 cmos output data d4 o 21 1 d5 cmos output data d5 o 22 1 d6 cmos output data d6 o 23 1 d7 cmos output data d7 o 24 1 d8 cmos output data d8 o 27 1 d9 cmos output data d9 o 28 1 d10 cmos output data d10 o 29 1 d11 cmos output data d11 o 30 1 d12 cmos output data d12 o 31 1 d13 cmos output data d13 o 32 1 indicates overvoltage on analog inputs (for differential input greater than full-scale), o 25 1 ovr cmos level drvdd digital supply i 1 1 digital ground. drgnd connect the pad to the ground plane. see board design considerations in the i pad 1 application information section. 22 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
pin configuration (lvds mode) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 rhb package (top view) figure 8. lvds mode pinout pin assignments ? lvds mode pin pin number pin name description type number of pins avdd analog power supply i 13, 15 2 agnd analog ground i 6, 9, 12 3 clkp, clkm differential clock inputs i 7, 8 2 inp, inm differential analog inputs i 10, 11 2 internal reference mode ? common-mode voltage output. vcm external reference mode ? reference input. the voltage forced on this pin sets the i/o 14 1 internal references. serial interface reset input. when using serial interface mode, the user must initialize the internal registers through a hardware reset by applying a high-going pulse on this pin or by using the reset software reset option. see the serial interface section. i 2 1 in parallel interface mode, the user has to tie the reset pin permanently high. (sclk, sdata, and sen are used as parallel pin controls in this mode.) the pin has an internal 100-k ? pull-down resistor. this pin functions as the serial interface clock input when reset is low. when reset is tied high, it controls coarse gain and internal/external reference sclk selection. tie sclk low for internal reference and 0 db gain and high for internal i 3 1 reference and 3.5 db gain. see table 1 . the pin has an internal 100-k ? pull-down resistor. this pin functions as the serial interface data input when reset is low. it controls various power down modes along with the pdn pin when reset is tied high. sdata i 4 1 see table 3 for detailed information. the pin has an internal 100 k ? pull-down resistor. the pin functions as the serial interface enable input when reset is low. when sen reset is high, it controls output interface type and data formats. see table 2 for i 5 1 detailed information. the pin has an internal 100-k ? pull-up resistor to drvdd. pdn global power-down control pin i 16 1 copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 23 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com pdn drvdd agnd inp clkoutm inm clkoutp agnd avdd avdd agnd clkp clkm 12 3 4 5 6 7 8 9 10 11 12 1314 15 16 d12_d13_p d12_d13_m d0_d1_p d10_d11_p d0_d1_m d10_d11_m d8_d9_p d8_d9_m reset d6_d7_p sclk d6_d7_m sdata d4_d5_p sen d4_d5_md2_d3_p d2_d3_m 2423 22 21 20 19 18 17 31 30 29 28 27 26 25 pad connected to drgnd 32 vcm
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 pin assignments ? lvds mode (continued) pin pin number pin name description type number of pins clkoutp differential output clock, true o 26 1 clkoutm differential output clock, complement o 25 1 d0_d1_p differential output data d0 and d1 multiplexed, true o 18 1 d0_d1_m differential output data d0 and d1 multiplexed, complement. o 17 1 d2_d3_p differential output data d2 and d3 multiplexed, true o 20 1 d2_d3_m differential output data d2 and d3 multiplexed, complement o 19 1 d4_d5_p differential output data d4 and d5 multiplexed, true o 22 1 d4_d5_m differential output data d4 and d5 multiplexed, complement o 21 1 d6_d7_p differential output data d6 and d7 multiplexed, true o 24 1 d6_d7_m differential output data d6 and d7 multiplexed, complement o 23 1 d8_d9_p differential output data d8 and d9 multiplexed, true o 28 1 d8_d9_m differential output data d8 and d9 multiplexed, complement o 27 1 d10_d11_p differential output data d10 and d11 multiplexed, true o 30 1 d10_d11_m differential output data d10 and d11 multiplexed, complement o 29 1 d12_d13_p differential output data d12 and d13 multiplexed, true o 32 1 d12_d13_m differential output data d12 and d13 multiplexed, complement o 31 1 drvdd digital supply i 1 1 digital ground. drgnd connect the pad to the ground plane. see board design considerations in application i pad 1 information section. 24 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
typical characteristics - ads6145 (f s = 125 msps) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) fft for 20 mhz input signal fft for 70 mhz input signal figure 9. figure 10. fft for 230 mhz input signal intermodulation distortion (imd) vs frequency figure 11. figure 12. sfdr vs input frequency snr vs input frequency figure 13. figure 14. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 25 product folder link(s): ads6145, ads6144 ads6143, ADS6142 f in ? input frequency ? mhz 64 68 72 76 80 84 88 92 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g005 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g006 gain = 0 db gain = 3.5 db www.ti.com f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude ? db g001 sfdr = 91.77 dbc sinad = 73.99 dbfssnr = 74.2 dbfs thd = 87.79 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude ? db g002 sfdr = 84.1 dbc sinad = 72.88 dbfssnr = 73.54 dbfs thd = 82.61 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude ? db g003 sfdr = 74.2 dbc sinad = 67.2 dbfssnr = 69.9 dbfs thd = 71.4 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 amplitude ? db g004 f in 1 = 190 mhz, 7 dbfs f in 2 = 185 mhz, 7 dbfs 2-t one imd = 83.5 dbfs sfdr = 81.3 dbfs
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ads6145 (f s = 125 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) sfdr vs input frequency (lvds interface) snr vs input frequency (lvds interface) figure 15. figure 16. sfdr vs input frequency across gains sinad vs input frequency across gains figure 17. figure 18. performance vs avdd performance vs drvdd figure 19. figure 20. 26 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 f in ? input frequency ? mhz 64 68 72 76 80 84 88 92 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g007 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g008 gain = 0 db gain = 3.5 db www.ti.com f in ? input frequency ? mhz 60 65 70 75 80 85 90 95 0 100 200 300 400 500 sfdr ? dbc g009 input adjusted to get ?1dbfs input 1 db 0 db 5 db 6 db 2 db 3 db 4 db f in ? input frequency ? mhz 60 62 64 66 68 70 72 74 76 0 100 200 300 400 500 sinad ? dbfs g010 2 db 5 db 1 db 0 db 4 db 6 db input adjusted to get ?1dbfs input 3 db snr ? dbfs drv dd ? supply v oltage ? v 86 88 90 92 94 96 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 sfdr ? dbc g012 f in = 10.1 mhz av dd = 3.3 v snr sfdr 71 72 73 74 75 76 av dd ? supply v oltage ? v 72 74 76 78 80 82 84 86 88 3.0 3.1 3.2 3.3 3.4 3.5 3.6 sfdr ? dbc g011 snr sfdr f in = 70.1 mhz drv dd = 3.3 v snr ? dbfs 70 71 72 73 74 75 76 77 78
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ads6145 (f s = 125 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) performance vs temperature performance vs input amplitude figure 21. figure 22. performance vs clock amplitude performance vs input clock duty cycle figure 23. figure 24. output noise histogram (inputs tied to common-mode) performance in external reference mode figure 25. figure 26. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 27 product folder link(s): ads6145, ads6144 ads6143, ADS6142 input clock duty cycle ? % 86 87 88 89 90 91 92 30 35 40 45 50 55 60 65 70 sfdr ? dbc g016 snr sfdr f in = 10.1 mhz snr ? dbfs 70 71 72 73 74 75 76 v vcm ? vcm v oltage ? v 83 85 87 89 91 93 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 f in = 20.1 mhz external reference mode sfdr ? dbc g018 snr sfdr snr ? dbfs 68 70 72 74 76 78 output code 0 5 10 15 20 25 30 35 40 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 occurence ? % g017 rms (lsb) = 1.1 www.ti.com t ? t emperature ? c 82 84 86 88 90 92 ?40 ?20 0 20 40 60 80 sfdr ? dbc g013 snr ? dbfs 72 73 74 75 76 77 f in = 10.1 mhz snr sfdr input amplitude ? dbfs 30 40 50 60 70 80 90 100 110 ?60 ?50 ?40 ?30 ?20 ?10 0 f in = 20.1 mhz sfdr ? dbc, dbfs g014 sfdr (dbc) sfdr (dbfs) snr (dbfs) 50 55 60 65 70 75 80 85 90 snr ? dbfs 76 78 80 82 84 86 88 90 92 0.5 1.0 1.5 2.0 2.5 3.0 sfdr ? dbc input clock amplitude ? v pp g015 snr sfdr f in = 20.1 mhz snr ? dbfs 72 73 74 75 76 77 78 79 80
typical characteristics - ads6144 (f s = 105 msps) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) fft for 20 mhz input signal fft for 80 mhz input signal figure 27. figure 28. fft for 230 mhz input signal intermodulation distortion (imd) vs frequency figure 29. figure 30. sfdr vs input frequency snr vs input frequency figure 31. figure 32. 28 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude ? db g019 sfdr = 88.6 dbc sinad = 74 dbfssnr = 74.3 dbfs thd = 87.4 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude ? db g020 sfdr = 84.6 dbc sinad = 73.1 dbfssnr = 73.7 dbfs thd = 82.7 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude ? db g021 sfdr = 74.9 dbc sinad = 66.5 dbfssnr = 67.9 dbfs thd = 73.3 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 amplitude ? db g022 f in 1 = 190 mhz, 7 dbfs f in 2 = 185 mhz, 7 dbfs 2-t one imd = 82.3 dbfs sfdr = 87.5 dbfs f in ? input frequency ? mhz 60 64 68 72 76 80 84 88 92 96 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g023 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g024 gain = 0 db gain = 3.5 db
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ads6144 (f s = 105 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) sfdr vs input frequency (lvds interface) snr vs input frequency (lvds interface) figure 33. figure 34. sfdr vs input frequency across gains sinad vs input frequency across gains figure 35. figure 36. performance vs avdd performance vs drvdd figure 37. figure 38. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 29 product folder link(s): ads6145, ads6144 ads6143, ADS6142 f in ? input frequency ? mhz 60 65 70 75 80 85 90 95 0 100 200 300 400 500 sfdr ? dbc g027 input adjusted to get ?1dbfs input 1 db 0 db 5 db 6 db 2 db 4 db 3 db f in ? input frequency ? mhz 60 62 64 66 68 70 72 74 76 0 100 200 300 400 500 sinad ? dbfs g028 2 db 5 db 1 db 0 db 3 db 4 db 6 db input adjusted to get ?1dbfs input av dd ? supply v oltage ? v 76 78 80 82 84 86 88 90 92 3.0 3.1 3.2 3.3 3.4 3.5 3.6 g029 f in = 70.1 mhz drv dd = 3.3 v sfdr ? dbc snr ? dbfs 72 73 74 75 76 77 78 79 80 snr sfdr snr ? dbfs drv dd ? supply v oltage ? v 88 90 92 94 96 98 100 102 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 sfdr ? dbc g030 f in = 10.1 mhz av dd = 3.3 v snr sfdr 70 71 72 73 74 75 76 77 www.ti.com f in ? input frequency ? mhz 60 64 68 72 76 80 84 88 92 96 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g025 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g026 gain = 0 db gain = 3.5 db
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ads6144 (f s = 105 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) performance vs temperature performance vs input amplitude figure 39. figure 40. performance vs clock amplitude performance vs input clock duty cycle figure 41. figure 42. output noise histogram with inputs tied to common-mode performance in external reference mode figure 43. figure 44. 30 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com 70 72 74 76 78 80 snr ? dbfs input amplitude ? dbfs 20 40 60 80 100 120 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr ? dbc, dbfs g032 f in = 20.1 mhz sfdr (dbc) sfdr (dbfs) snr (dbfs) t ? t emperature ? c 83 85 87 89 91 93 ?40 ?20 0 20 40 60 80 sfdr ? dbc g031 snr ? dbfs 72 73 74 75 76 77 f in = 10.1 mhz snr sfdr 76 78 80 82 84 86 88 90 92 0.5 1.0 1.5 2.0 2.5 3.0 sfdr ? dbc input clock amplitude ? v pp g033 snr sfdr f in = 20.1 mhz snr ? dbfs 72 73 74 75 76 77 78 79 80 input clock duty cycle ? % 80 82 84 86 88 90 92 94 96 30 35 40 45 50 55 60 65 70 sfdr ? dbc g034 snr ? dbfs 71 72 73 74 75 76 77 78 79 snr sfdr f in = 10.1 mhz v vcm ? vcm v oltage ? v 86 88 90 92 94 96 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 f in = 20.1 mhz external reference mode sfdr ? dbc g036 snr sfdr snr ? dbfs 68 70 72 74 76 78 output code 0 5 10 15 20 25 30 35 40 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 occurence ? % g035 rms (lsb) = 1.049
typical characteristics - ads6143 (f s = 80 msps) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) fft for 20 mhz input signal fft for 70 mhz input signal figure 45. figure 46. fft for 230 mhz input signal intermodulation distortion (imd) vs frequency figure 47. figure 48. sfdr vs input frequency snr vs input frequency figure 49. figure 50. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 31 product folder link(s): ads6145, ads6144 ads6143, ADS6142 f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 amplitude ? db g038 sfdr = 83.5 dbc sinad = 73.4 dbfssnr = 74.3 dbfs thd = 82.6 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 amplitude ? db g039 sfdr = 81.2 dbc sinad = 70.4 dbfssnr = 71.4 dbfs thd = 78 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 amplitude ? db g040 f in 1 = 190 mhz, 7 dbfs f in 2 = 185 mhz, 7 dbfs 2-t one imd = 84 dbfs sfdr = 89 dbfs www.ti.com f in ? input frequency ? mhz 60 64 68 72 76 80 84 88 92 96 100 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g041 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g042 gain = 0 db gain = 3.5 db f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 amplitude ? db g037 sfdr = 89.8 dbc sinad = 74.5 dbfssnr = 74.8 dbfs thd = 87 dbc
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ads6143 (f s = 80 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) sfdr vs input frequency (lvds interface) snr vs input frequency (lvds interface) figure 51. figure 52. sfdr vs input frequency across gains sinad vs input frequency across gains figure 53. figure 54. performance vs avdd performance vs drvdd figure 55. figure 56. 32 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 av dd ? supply v oltage ? v 72 74 76 78 80 82 84 86 88 3.0 3.1 3.2 3.3 3.4 3.5 3.6 sfdr ? dbc g047 snr sfdr f in = 70.1 mhz drv dd = 3.3 v snr ? dbfs 70 71 72 73 74 75 76 77 78 www.ti.com f in ? input frequency ? mhz 60 64 68 72 76 80 84 88 92 96 100 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g043 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g044 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 60 65 70 75 80 85 90 95 0 100 200 300 400 500 sfdr ? dbc g045 input adjusted to get ?1dbfs input 1 db 0 db 5 db 6 db 2 db 3 db 4 db f in ? input frequency ? mhz 60 62 64 66 68 70 72 74 76 0 100 200 300 400 500 sinad ? dbfs g046 2 db 5 db 1 db 0 db 3 db 4 db 6 db input adjusted to get ?1dbfs input snr ? dbfs drv dd ? supply v oltage ? v 88 90 92 94 96 98 100 102 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 sfdr ? dbc g048 f in = 10.1 mhz av dd = 3.3 v snr sfdr 70 71 72 73 74 75 76 77
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ads6143 (f s = 80 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) performance vs temperature performance vs input amplitude figure 57. figure 58. performance vs clock amplitude performance vs input clock duty cycle figure 59. figure 60. output noise histogram with inputs tied to common-mode performance in external reference mode figure 61. figure 62. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 33 product folder link(s): ads6145, ads6144 ads6143, ADS6142 t ? t emperature ? c 85 87 89 91 93 95 ?40 ?20 0 20 40 60 80 sfdr ? dbc g049 72 73 74 75 76 77 snr ? dbfs f in = 10.1 mhz sfdr snr input amplitude ? dbfs 30 40 50 60 70 80 90 100 110 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr ? dbc, dbfs g050 sfdr (dbc) sfdr (dbfs) snr (dbfs) 50 55 60 65 70 75 80 85 90 snr ? dbfs f in = 20 mhz input clock duty cycle ? % 80 82 84 86 88 90 92 94 96 30 35 40 45 50 55 60 65 70 sfdr ? dbc g052 snr ? dbfs 72 73 74 75 76 77 78 79 80 snr sfdr f in = 10.1 mhz www.ti.com 76 78 80 82 84 86 88 90 92 0.5 1.0 1.5 2.0 2.5 3.0 sfdr ? dbc input clock amplitude ? v pp g051 snr sfdr f in = 20.1 mhz snr ? dbfs 72 73 74 75 76 77 78 79 80 v vcm ? vcm v oltage ? v 82 84 86 88 90 92 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 f in = 20.1 mhz external reference mode sfdr ? dbc g054 snr sfdr snr ? dbfs 72 74 76 78 80 82 output code 0 5 10 15 20 25 30 35 40 8204 8205 8206 8207 8208 8209 8210 8211 8212 8213 occurence ? % g053 rms (lsb) = 1.037
typical characteristics - ADS6142 (f s = 65 msps) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) fft for 20 mhz input signal fft for 90 mhz input signal figure 63. figure 64. fft for 230 mhz input signal intermodulation distortion (imd) vs frequency figure 65. figure 66. sfdr vs input frequency snr vs input frequency figure 67. figure 68. 34 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 amplitude ? db g058 f in 1 = 190 mhz, 7 dbfs f in 2 = 185 mhz, 7 dbfs 2-t one imd = 88 dbfs sfdr = 92 dbfs f in ? input frequency ? mhz 60 64 68 72 76 80 84 88 92 96 100 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g059 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g060 gain = 0 db gain = 3.5 db www.ti.com f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 amplitude ? db g055 sfdr = 91.3 dbc sinad = 74.8 dbfssnr = 75 dbfs thd = 89.5 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 amplitude ? db g056 sfdr = 83 dbc sinad = 73.5 dbfssnr = 74.4 dbfs thd = 82.2 dbc f ? frequency ? mhz ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 amplitude ? db g057 sfdr = 83 dbc sinad = 71.2 dbfssnr = 71.9 dbfs thd = 79.8 dbc
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ADS6142 (f s = 65 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) sfdr vs input frequency (lvds interface) snr vs input frequency (lvds interface) figure 69. figure 70. sfdr vs input frequency across gains sinad vs input frequency across gains figure 71. figure 72. performance vs avdd performance vs drvdd figure 73. figure 74. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 35 product folder link(s): ads6145, ads6144 ads6143, ADS6142 f in ? input frequency ? mhz 60 64 68 72 76 80 84 88 92 96 100 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g061 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g062 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 60 65 70 75 80 85 90 95 0 100 200 300 400 500 sfdr ? dbc g063 input adjusted to get ?1dbfs input 1 db 0 db 5 db 2 db 3 db 4 db 6 db www.ti.com f in ? input frequency ? mhz 60 62 64 66 68 70 72 74 76 0 100 200 300 400 500 sinad ? dbfs g064 2 db 5 db 1 db 0 db 4 db 6 db input adjusted to get ?1dbfs input 3 db av dd ? supply v oltage ? v 80 82 84 86 88 90 92 94 96 3.0 3.1 3.2 3.3 3.4 3.5 3.6 sfdr ? dbc g065 snr sfdr f in = 70.1 mhz drv dd = 3.3 v snr ? dbfs 72 73 74 75 76 77 78 79 80 snr ? dbfs drv dd ? supply v oltage ? v 92 94 96 98 100 102 104 106 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 sfdr ? dbc g066 f in = 10.1 mhz av dd = 3.3 v snr sfdr 70 71 72 73 74 75 76 77
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 typical characteristics - ADS6142 (f s = 65 msps) (continued) all plots are at 25 c, avdd = drvdd = 3.3 v, maximum rated sampling frequency, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) performance vs temperature performance vs input amplitude figure 75. figure 76. performance vs clock amplitude performance vs input clock duty cycle figure 77. figure 78. output noise histogram with inputs tied to common-mode performance in external reference mode figure 79. figure 80. 36 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 snr ? dbfs 72 73 74 75 76 77 78 t ? t emperature ? c 86 88 90 92 94 96 98 ?40 ?20 0 20 40 60 80 sfdr ? dbc g067 f in = 10.1 mhz snr sfdr 80 82 84 86 88 90 92 94 96 0.5 1.0 1.5 2.0 2.5 3.0 sfdr ? dbc input clock amplitude ? v pp g069 snr sfdr f in = 20.1 mhz snr ? dbfs 72 73 74 75 76 77 78 79 80 snr ? dbfs 70 71 72 73 74 75 76 77 input clock duty cycle ? % 70 74 78 82 86 90 94 98 30 35 40 45 50 55 60 65 70 sfdr ? dbc g070 snr sfdr f in = 10.1 mhz snr ? dbfs 72 74 76 78 80 82 v vcm ? vcm v oltage ? v 85 87 89 91 93 95 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 sfdr ? dbc g072 f in = 20.1 mhz external reference mode snr sfdr output code 0 5 10 15 20 25 30 35 40 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 occurence ? % g071 rms (lsb) = 1.041 www.ti.com input amplitude ? dbfs 30 40 50 60 70 80 90 100 110 ?60 ?50 ?40 ?30 ?20 ?10 0 f in = 20.1 mhz sfdr ? dbc, dbfs g068 sfdr (dbc) sfdr (dbfs) snr (dbfs) 50 55 60 65 70 75 80 85 90 snr ? dbfs
typical characteristics - low sampling frequencies f s = 40 msps f s = 25 msps ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 all plots are at 25 c, avdd = drvdd = 3.3 v, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) sfdr vs input frequency snr vs input frequency figure 81. figure 82. sfdr vs input frequency snr vs input frequency figure 83. figure 84. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 37 product folder link(s): ads6145, ads6144 ads6143, ADS6142 f in ? input frequency ? mhz 60 64 68 72 76 80 84 88 92 96 100 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g073 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g074 gain = 0 db gain = 3.5 db www.ti.com f in ? input frequency ? mhz 50 60 70 80 90 100 0 50 100 150 200 250 300 350 400 450 500 sfdr ? dbc g075 gain = 0 db gain = 3.5 db f in ? input frequency ? mhz 62 64 66 68 70 72 74 76 0 50 100 150 200 250 300 350 400 450 500 snr ? dbfs g076 gain = 0 db gain = 3.5 db
common plots ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 all plots are at 25 c, avdd = drvdd = 3.3 v, sine wave input clock, 1.5 v pp differential clock amplitude, 50% clock duty cycle, ? 1 dbfs differential analog input, internal reference mode, 0 db gain, cmos output interface (unless otherwise noted) power dissipation vs common-mode rejection ratio vs frequency sampling frequency (ddr lvds and cmos) figure 85. figure 86. drvdd current vs sampling frequency across load capacitance (cmos) figure 87. 38 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 f s ? sampling frequency ? msps 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 25 50 75 100 125 p d ? power dissipation ? w g078 lvds cmos f in = 2.5 mhz c l = 5 pf f s ? sampling frequency ? msps 0 5 10 15 20 25 30 0 25 50 75 100 125 drv dd current ? ma g079 1.8 v , 5 pf 3.3 v , 5 pf 3.3 v , 10 pf 1.8 v , no load 3.3 v , no load www.ti.com f ? frequency ? mhz ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 50 100 150 200 250 300 cmrr ? dbc g077
contour plots across input and sampling frequencies ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 88. sfdr contour (no gain, f s = 2 v pp ) figure 89. sfdr contour (with 3.5 db coarse gain, f s = 1.34 v pp ) copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 39 product folder link(s): ads6145, ads6144 ads6143, ADS6142 10 50 100 150 f - input frequency - mhz in f - sampling frequency - msps s sfdr - dbc 200 250 300 400 450 350 500 25 30 40 50 100 60 70 80 90 110 120 125 60 65 75 m0049-15 87 87 87 87 90 84 84 81 81 84 84 84 84 84 78 72 75 75 75 69 72 72 69 66 69 66 66 80 85 70 90 95 90 90 90 93 78 81 81 78 78 63 63 60 60 63 75 10 50 100 150 f - input frequency - mhz in f - sampling frequency - msps s sfdr - dbc 200 250 300 400 450 350 500 25 30 40 50 100 60 70 80 90 110 120 125 60 65 75 m0049-16 87 87 87 87 87 87 90 84 81 81 84 84 84 78 72 75 75 75 69 72 72 69 66 69 66 80 85 70 90 95 90 90 90 90 93 93 93 93 78 81 81 78 78 63 75 87 90 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 contour plots across input and sampling frequencies (continued) figure 90. snr contour (no gain, f s = 2 v pp ) figure 91. snr contour (with 3.5 db coarse gain, f s = 1.34 v pp ) 40 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 10 50 100 150 f - input frequency - mhz in f - sampling frequency - msps s snr - dbfs 200 250 300 400 450 350 500 25 30 40 50 100 60 70 80 90 110 120 125 64 66 68 m0048-15 73 73 73 71 71 71 71 72 72 72 70 70 70 70 69 69 69 69 68 68 68 68 67 67 67 66 66 65 64 74 74 74 75 70 72 74 10 50 100 150 f - input frequency - mhz in f - sampling frequency - msps s snr - dbfs 200 250 300 400 450 350 500 25 30 40 50 100 60 70 80 90 110 120 125 64 66 68 m0048-16 73 73 73 71 71 71 72 72 72 70 70 70 70 69 69 69 69 68 68 68 68 67 67 67 66 66 65 64 70 72 74 www.ti.com
application information theory of operation analog input ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the ads614x devices are a family of low power, 14-bit pipeline adcs in a cmos process with up to a 125 msps sampling frequencies. these devices are based on switched capacitor technology and run off a single 3.3-v supply. the conversion process is initiated by the rising edge of the external input clock. once the signal is captured by the input sample and hold, the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. at every clock edge, the sample propagates through the pipeline resulting in a data latency of 9 clock cycles. the output is available as 14-bit data, in ddr lvds or cmos and coded in either straight offset binary or binary 2s complement format. the analog input consists of a switched-capacitor based differential sample and hold architecture, shown in figure 92 . this differential topology results in good ac-performance even for high input frequencies at high sampling rates. the inp and inm pins have to be externally biased around a common-mode voltage of 1.5 v available on the vcm pin. for a full-scale differential input, each input pin (inp, inm) has to swing symmetrically between vcm + 0.5 v and vcm ? 0.5 v, resulting in a 2v pp differential input swing. the maximum swing is determined by the internal reference voltages refp (2.5 v nominal) and refm (0.5 v, nominal). figure 92. input stage the input sampling circuit has a high 3db bandwidth that extends up to 450 mhz (measured from the input pins to the voltage across the sampling capacitors). copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 41 product folder link(s): ads6145, ads6144 ads6143, ADS6142 resr 200 w lpkg nh ? 1 25 w sampling capacitor csamp 4.0 pf inp inm cbond pf ? 1 50 w cpar1 0.8 pf cpar2 1 pf ron 15 w ron 10 w ron 15 w cpar2 1 pf 50 w 3.2 pf lpkg 1 nh ? 25 w cbond pf ? 1 resr 200 w csamp 4.0 pf sampling capacitor sampling switch sampling switch rcr filter www.ti.com
drive circuit requirements ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 93. adc analog input bandwidth for optimum performance, the analog inputs must be driven differentially. this improves the common-mode noise immunity and even-order harmonic rejection. a 5- ? resistor in series with each input pin is recommended to damp out ringing caused by the package parasitics. it is also necessary to present low impedance (< 50 ? ) for the common-mode switching currents. for example, this is achieved by using two resistors from each input terminated to the common-mode voltage (vcm). in addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency range and matched impedance to the source. while doing this, the adc input impedance (zin) must be considered. over a wide frequency range, the input impedance can be approximated by a parallel combination of rin and cin (zin = rin||cin). figure 94. adc input resistance, rin 42 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 f in ? input frequency ? mhz ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 0 100 200 300 400 500 600 magnitude ? db g080 www.ti.com f ? frequency ? mhz 0 100 200 300 400 500 600 r ? resistance ? k w 100 10 0.1 0.01 g083 1
using rf-transformer based drive circuits ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 95. adc input capacitance, cin figure 96 shows a configuration using a single 1:1 turn ratio transformer (for example, coilcraft wbc1-1) that can be used for low input frequencies (about 100 mhz). the single-ended signal is fed to the primary winding of the rf transformer. the transformer is terminated on the secondary side. putting the termination on the secondary side helps to shield the kickbacks caused by the sampling circuit from the rf transformer ? s leakage inductances. the termination is accomplished by two resistors connected in series, with the center point connected to the 1.5 v common mode (vcm pin). the value of the termination resistors (connected to common mode) has to be low (< 100 ? ) to provide a low-impedance path for the adc common-mode switching current. figure 96. single transformer drive circuit at high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. connecting two identical rf transformers back-to-back helps minimize this mismatch, and good performance is obtained for high frequency input signals. figure 97 shows an example using two transformers (coilcraft wbc1-1). an additional termination resistor pair (enclosed within the dotted box in figure 97 ) may be required between the two transformers to improve the balance between the p and m sides. the center point of this termination must be connected to ground. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 43 product folder link(s): ads6145, ads6144 ads6143, ADS6142 inp inmvcm 1 : 1 5 w 0.1 m f 0.1 m f 25 w tf_adc 25 w 5 w www.ti.com f ? frequency ? mhz 0 1 2 3 4 5 6 7 8 9 0 100 200 300 400 500 600 c ? capacitance ? pf g084
using differential amplifier drive circuits ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 97. two transformer drive circuit figure 98 shows a drive circuit using a differential amplifier (ti's ths4509) to convert a single-ended input to a differential output that can be interfaced to the adc analog input pins. in addition to the single-ended to differential conversion, the amplifier also provides gain (10 db in figure 98 ). r fil helps to isolate the amplifier outputs from the switching input of the adc. together with c fil it also forms a low-pass filter that band-limits the noise (and signal) at the adc input. as the amplifier output is ac-coupled, the common-mode voltage of the adc input pins is set using two 200- ? resistors connected to vcm. the amplifier output can also be dc-coupled. using the output common-mode control of the ths4509, the adc input pins can be biased to 1.5 v. in this case, use +4-v and ? 1-v supplies for the ths4509 so that its output common-mode voltage (1.5 v) is at mid-supply. figure 98. drive circuit using the ths4509 see the evm user guide (slwu028 ) for more information. 44 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com inp inm vcm 1:1 5 w 0 .1 m f 1:1 50 w 50 w 0 .1 m f 50 w 50 w 5 w r g r f r f r fil r fil c fil c fil r g 0.1 f m 0.1 f m 0.1 f m 0.1 f m 0.1 f m 0.1 f m 0.1 f m 10 f m 10 f m r s r s t || r r t +v s cm inp inm ads614x ths4509 vcm 500 w 200 w 200 w 5 w 5 w 500 w 0.1 f m Cv s
input common mode (1) reference internal reference external reference (2) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 to ensure a low-noise common-mode reference, the vcm pin is filtered with a 0.1- m f low-inductance capacitor connected to ground. the vcm pin is designed to directly drive the adc inputs. the input stage of the adc sinks a common-mode current in the order of 180 m a (at 125 msps). equation 1 describes the dependency of the common-mode current and the sampling frequency. equation 1 helps to design the output capability and impedance of the cm driving circuit. the ads614x have built-in internal references refp and refm, requiring no external components. design schemes are used to linearize the converter load seen by the references; this and the integration of the requisite reference capacitors on-chip eliminates the need for external decoupling. the full-scale input range of the converter is controlled in the external reference mode as explained below. the internal or external reference modes can be selected by programming the serial interface register bit (table 5 ). figure 99. reference section when the device is in internal reference mode, the refp and refm voltages are generated internally. common-mode voltage (1.5 v nominal) is output on the vcm pin, which can be used to externally bias the analog input pins. when the device is in external reference mode, vcm acts as a reference input pin. the voltage forced on the vcm pin is buffered and gained by 1.33 internally, generating the refp and refm voltages. the differential input voltage corresponding to full-scale is given by equation 2 . in this mode, the 1.5-v common-mode voltage to bias the input pins has to be generated externally. there is no change in performance compared to internal reference mode. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 45 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com fs 180 a x 125 msps m vcm refm refp intref intref extref internal reference 1 k w 4 k w full?scale differential input pp (voltage forced on vcm) 1.33
coarse gain and programmable fine gain ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the ads614x include gain settings that can be used to improve sfdr performance (compared to 0 db gain mode). the gain settings are 3.5 db coarse gain and 0 db to 6 db programmable fine gain. for each gain setting, the analog input full-scale range scales proportionally, as shown in table 13 . the coarse gain is a fixed setting of 3.5 db and is designed to improve sfdr with little degradation in snr (as shown in figure 13 and figure 14 ). the fine gain is programmable in 1 db steps from 0 db to 6 db. with fine gain, sfdr improvement is also achieved, but at the expense of snr (there is about 1 db snr degradation for every 1 db of fine gain). so, the fine gain can be used to trade-off between sfdr and snr. the coarse gain makes it possible to get the best sfdr but without losing snr significantly. at high input frequencies, the gains are especially useful as the sfdr improvement is significant with marginal degradation in sinad. the gains can be programmed using the register bits (see table 5 ) and (see table 10 ). note that the default gain after reset is 0 db. table 13. full-scale range across gains gain, db type full-scale range, v pp 0 default after reset 2.00 3.5 coarse setting (fixed) 1.34 1 1.78 2 1.59 3 1.42 fine gain (programmable) 4 1.26 5 1.12 6 1.00 46 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
clock input ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the clock inputs of the ads614x can be driven differentially (sine, lvpecl, or lvds) or single-ended (lvcmos), with little or no difference in performance between configurations. the common-mode voltage of the clock inputs is set to vcm using internal 5-k ? resistors as shown in figure 100 . this allows the use of transformer-coupled drive circuits for the sine wave clock, or ac-coupling for the lvpecl, lvds clock sources (see figure 102 and figure 103 ). for best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to common-mode noise. in this case, it is best to connect both clock inputs to the differential input clock signal with 0.1- m f capacitors, as shown in figure 102 . a single-ended cmos clock can be ac-coupled to the clkp input, with clkm connected to ground with a 0.1- m f capacitor, as shown in figure 103 . for high input frequency sampling, a clock source with very low jitter is recommended. band-pass filtering of the clock source can help reduce the effect of jitter. there is no change in performance with a non-50% duty cycle clock input. figure 24 shows the performance of the adc versus clock duty cycle. figure 100. internal clock buffer copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 47 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com clkp 5 k w vcm 5 k w 6 pf 10 w 10 w clkm clock buffer ceq ceq ceq 1 to 3 pf, equivalent input capacitance of clock buffer ? lpkg 1 nh ? lpkg 1 nh ? cbond 1 pf ? cbond 1 pf ? resr 100 ? w resr 100 ? w
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 101. clock buffer input impedance figure 102. differential clock driving circuit figure 103. single-ended clock driving circuit 48 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 clkpclkm cmos clock input ads614x 0.1 f m 0.1 f m www.ti.com clock frequency ? mhz 0 100 200 300 400 500 600 700 800 900 1000 0 25 50 75 100 125 impedance (magnitude) ? w g082 clkpclkm differential sine-wave or pecl or lvds clock input ads614x 0.1 f m 0.1 f m
power-down modes global power down standby output buffer disable input clock stop power supply sequence ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the ads614x have four power-down modes ? global power down, standby, output buffer disable, and input clock stopped. these modes can be set using the serial interface or using the parallel interface (pins sdata and pdn). table 14. power-down modes power-down parallel interface serial interface total power, wake-up time modes register bit mw (to valid data) sdata pdn (table 5 ) normal operation low low =0 and 417 - =0 standby low high =0 and 72 slow (15 m s) =1 output buffer disable high low =1 and 408 fast (200 ns) =0 global power down high high =1 and 30 slow (15 m s) =1 in this mode, the a/d converter, internal references, and the output buffers are powered down and the total power dissipation reduces to about 30 mw. the output buffers are in a high-impedance state. the wake-up time from the global power down to output data becoming valid in normal mode is a maximum of 50 m s. note that after coming out of global power down, optimum performance is achieved after the internal reference voltages have stabilized (about 1 ms). only the a/d converter is powered down and total power dissipation is approximately 72 mw. the wake-up time from standby to output data becoming valid is a maximum of 50 m s. the data output buffers can be disabled, reducing total power to about 408 mw. with the buffers disabled, the outputs are in a high-impedance state. the wake-up time from this mode to data becoming valid in normal mode is a maximum of 500 ns in lvds mode and 200 ns in cmos mode. the converter enters this mode when the input clock frequency falls below 1 msps. power dissipation is approximately 120 mw, and the wake-up time from this mode to data becoming valid in normal mode is a maximum of 50 m s. during power-up, the avdd and drvdd supplies can come up in any sequence. the two supplies are separated inside the device. externally, they can be driven from separate supplies or from a single supply. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 49 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
digital output interface parallel cmos interface ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the ads614x output 14 data bits together with an output clock. the output interface is either parallel cmos or ddr lvds voltage levels and can be selected using the serial register bit or parallel pin sen. in cmos mode, the output buffer supply (drvdd) can be operated over a wide range from 1.8 v to 3.3 v (typical). each data bit is output on a separate pin as a cmos voltage level, every clock cycle. for drvdd 2.2 v, it is recommended to use the cmos output clock (clkout) to latch data in the receiving chip. the rising edge of clkout can be used to latch data in the receiver, even at the highest sampling speed (125 msps). it is recommended to minimize the load capacitance seen by the data and clock output pins by using short traces to the receiver. also, match the output data and clock traces to minimize the skew between them. for drvdd < 2.2 v, it is recommended to use an external clock (for example, input clock delayed to get desired setup/hold times). output clock position programmability there is an option to shift (delay) the output clock position so that the setup time increases by 400 ps (typical, with respect to the default timings specified). this may be useful if the receiver needs more setup time, especially at high sampling frequencies. this can be programmed using the serial interface register bit (table 6 ). output buffer strength programmability switching noise (caused by cmos output data transitions) can couple into the analog inputs during the instant of sampling and degrade the snr. the coupling and snr degradation increases as the output buffer drive is made stronger. to minimize this, the ads614x cmos output buffers are designed with a controlled drive strength for the best snr. the default drive strength also ensures a wide data stable window for load capacitances up to 5 pf and a drvdd supply voltage 2.2 v. to ensure a wide data stable window for load capacitances > 5 pf, there is an option to increase the drive strength using the serial interface ( , see table 12 ). note that for a drvdd supply voltage < 2.2 v, it is recommended to use the maximum drive strength (for any value of load capacitance). cmos mode power dissipation with cmos outputs, the drvdd current scales with the sampling frequency and the load capacitance on every output pin. the maximum drvdd current occurs when each output bit toggles between 0 and 1 every clock cycle. in actual applications, this condition is unlikely to occur. the actual drvdd current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal. digital current due to cmos output switching = c l drvdd x (n x f avg ) where c l = load capacitance, n f avg = average number of output bits switching figure 87 shows the current with various load capacitances across sampling frequencies with a 2-mhz analog input frequency. 50 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 104. cmos output buffers copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 51 product folder link(s): ads6145, ads6144 ads6143, ADS6142 d0d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 ads614x pins d12d13 clkout 14 bit adc data ovr cmos output buffers www.ti.com
ddr lvds interface ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the lvds interface works only with a 3.3-v drvdd supply. in this mode, the 14 data bits and the output clock are available as lvds (low voltage differential signal) levels. two successive data bits are multiplexed and output on each lvds differential pair every clock cycle (ddr - double data rate, see figure 105 ). so, there are 7 lvds output pairs for the 14 data bits and 1 lvds output pair for the output clock. lvds buffer current programmability the default lvds buffer output current is 3.5 ma. when terminated by 100 ? , this results in a 350-mv single-ended voltage swing (700-mv pp differential swing). the lvds buffer currents can also be programmed to 2.5 ma, 4.5 ma, and 1.75 ma (register bits , see table 11 ). in addition, there is a current double mode, where this current is doubled for the data and output clock buffers (register bits , see table 11 ). figure 105. ddr lvds outputs 52 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 clkoutp clkoutm d0_d1_p d0_d1_m d2_d3_p d2_d3_m d4_d5_p d4_d5_m d6_d7_p d6_d7_m d8_d9_p d8_d9_m d10_d11_p d10_d11_m output clock data bits d0, d1 data bits d2, d3 data bits d4, d5 data bits d6, d7 data bits d8, d9 data bits d10, d11 ads614x pins d12_d13_p d12_d13_m data bits d12, d13 14-bit adc data lvds buffers www.ti.com
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 even data bits d0, d2, d4, d6, d8, d10, and d12 are output at the rising edge of clkoutp and the odd data bits d1, d3, d5, d7, d9, d11, and d13 are output at the falling edge of clkoutp. both the rising and falling edges of clkoutp must be used to capture all 14 data bits (see figure 106 ). figure 106. ddr lvds interface lvds buffer internal termination an internal termination option is available (using the serial interface), by which the lvds buffers are differentially terminated inside the device. the termination resistances available are ? 300 ? , 185 ? , and 150 ? (nominal with 20% variation). any combination of these three terminations can be programmed; the effective termination is the parallel combination of the selected resistances. this results in eight effective terminations from open (no termination) to 65 ? . the internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. with 100- ? internal and 100- ? external termination, the voltage swing at the receiver end is halved (compared to no internal termination). the voltage swing can be restored by using the lvds current double mode. figure 107 and figure 108 compare the lvds eye diagrams without and with internal termination (100 ? ). with internal termination, the eye looks clean even with 10-pf load capacitance (from each output pin to ground). the termination is programmed using register bits and (see table 11 ). copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 53 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com clkoutp d0_d1_p, d0_d1_m d2_d3_p, d2_d3_m d4_d5_p, d4_d5_m d6_d7_p, d6_d7_m d8_d9_p, d8_d9_m d10_d11_p, d10_d11_m d12_d13_p, d12_d13_m d0d2 d4 d6 d8 d10d12 sample n+1 sample n d0d2 d4 d6 d8 d10d12 d1d3 d5 d7 d9 d11 d13 d1d3 d5 d7 d9 d11 d13 clkoutm
output data format output timings ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 figure 107. lvds eye diagram - no internal termination figure 108. lvds eye diagram with 100- ? internal 5-pf load capacitance termination blue trace - output clock (clkout) 10-pf load capacitance pink trace - output data blue trace - output clock (clkout) pink trace - output data two output data formats are supported ? 2s complement and offset binary. they can be selected using the parallel control pin sen or the serial interface register bit (see table 8 ). the tables below show the timings at lower sampling frequencies. table 15. timing characteristics at lower sampling frequencies (1) (2) t su data setup time, ns t h data hold time, ns t pdi clock propagation delay, ns f s , msps min typ max min typ max min typ max cmos interface, drvdd = 2.5 v to 3.3 v 40 11.3 12.8 10 11.2 5 6.5 7.9 20 23 25 21 23 10 48 50 46 48 ddr lvds interface, drvdd = 3.3 v 40 10.2 10.8 0.7 1.7 4.3 5.8 7.3 20 22 23 0.7 1.7 4.5 6.5 8.5 10 47 48 0.7 1.7 4.5 6.5 8.5 (1) timing parameters are specified by design and characterization and not tested in production. (2) timings are specified with default output buffer drive strength and c l = 5 pf. 54 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
board design considerations grounding supply decoupling exposed thermal pad ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 a single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of the board are cleanly partitioned. see the evm user guide (slwu028 ) for details on layout and grounding. as the ads614x already include internal decoupling, minimal external decoupling can be used without loss in performance. note that decoupling capacitors can help filter external power supply noise, so the optimum number of capacitors would depend on the actual application. the decoupling capacitors should be placed very close to the converter supply pins. it is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching noise from sensitive analog circuitry. in case only a single 3.3-v supply is available, it should be routed first to avdd. it can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being routed to drvdd. it is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal performance. for detailed information, see application notes qfn layout guidelines (sloa122 ) and qfn/son pcb attachment (slua271 ). copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 55 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
definition of specifications analog bandwidth aperture delay aperture uncertainty (jitter) clock pulse width/duty cycle maximum conversion rate minimum conversion rate differential nonlinearity (dnl) integral nonlinearity (inl) gain error offset error temperature drift ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 the analog input frequency at which the power of the fundamental is reduced by 3 db with respect to the low frequency value. the delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. the sample-to-sample variation in aperture delay. the duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. duty cycle is typically expressed as a percentage. a perfect differential sine-wave clock results in a 50% duty cycle. the maximum sampling rate at which certified operation is given. all parametric testing is performed at this sampling rate unless otherwise noted. the minimum sampling rate at which the adc functions. an ideal adc exhibits code transitions at analog input values spaced exactly 1 lsb apart. the dnl is the deviation of any single step from this ideal value, measured in units of lsbs. the inl is the deviation of the adc ? s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsbs. the gain error is the deviation of the adc ? s actual input full-scale range from its ideal value. the gain error is given as a percentage of the ideal input full-scale range. the offset error is the difference, given in number of lsbs, between the adc ? s actual average idle channel output code and the ideal average idle channel output code. this quantity is often mapped into mv. the temperature drift coefficient (with respect to gain error and offset error) specifies the change per degree celsius of the parameter from t min to t max . it is calculated by dividing the maximum deviation of the parameter across the t min to t max range by the difference t max ? t min . 56 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
signal-to-noise ratio (4) signal-to-noise and distortion (sinad) (5) effective number of bits (enob) (6) total harmonic distortion (thd) (7) spurious-free dynamic range (sfdr) two-tone intermodulation distortion dc power supply rejection ratio (dc psrr) ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 snr is the ratio of the power of the fundamental (p s ) to the noise floor power (p n ), excluding the power at dc and the first nine harmonics. snr is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter ? s full-scale range. sinad is the ratio of the power of the fundamental (p s ) to the power of all the other spectral components including noise (p n ) and distortion (p d ), but excluding dc. sinad is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter ? s full-scale range. the enob is a measure of a converter ? s performance as compared to the theoretical limit based on quantization noise. thd is the ratio of the power of the fundamental (p s ) to the power of the first nine harmonics (p d ). thd is typically given in units of dbc (db to carrier). the ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). sfdr is typically given in units of dbc (db to carrier). imd3 is the ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at either frequency 2f1 ? f2 or 2f2 ? f1. imd3 is either given in units of dbc (db to carrier) when the absolute power of the fundamental is used as the reference, or dbfs (db to full scale) when the power of the fundamental is extrapolated to the converter ? s full-scale range. the dc pssr is the ratio of the change in offset error to a change in analog supply voltage. the dc psrr is typically given in units of mv/v. copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 57 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com snr 10log 10 p s p n sinad 10log 10 p s p n p d enob sinad 1.76 6.02 thd 10log 10 p s p n
ac power supply rejection ratio (ac psrr) (8) common-mode rejection ratio (cmrr) (9) voltage overload recovery ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 ac psrr is the measure of rejection of variations in the supply voltage of the adc. if v sup is the change in the supply voltage and v out is the resultant change in the adc output code (referred to the input), then cmrr is the measure of rejection of variations in the input common-mode voltage of the adc. if vcm is the change in the input common-mode voltage and v out is the resultant change in the adc output code (referred to the input), then the number of clock cycles taken to recover to less than 1% error for a 6-db overload on the analog inputs. a 6-dbfs sine wave at nyquist frequency is used as the test stimulus. 58 submit documentation feedback copyright ? 2007 ? 2008, texas instruments incorporated product folder link(s): ads6145, ads6144 ads6143, ADS6142 (expressed in dbc) d v cm d v out 10 cmrr = 20log www.ti.com (expressed in dbc) d v sup d v out 10 psrr = 20log
ads6145, ads6144 ads6143, ADS6142 slws198b ? july 2007 ? revised march 2008 revision history changes from revision a (october 2007) to revision b ............................................................................................... page added maximum drvdd current footnote ........................................................................................................................... 5 added sclk and sen pin function footnote ......................................................................................................................... 8 changed ddr lvds output data sequence in figure 1 ..................................................................................................... 11 changed pin configuration (cmos mode) information ........................................................................................................ 21 changed pin configuration (lvds mode) information ......................................................................................................... 23 copyright ? 2007 ? 2008, texas instruments incorporated submit documentation feedback 59 product folder link(s): ads6145, ads6144 ads6143, ADS6142 www.ti.com
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ADS6142irhbr active vqfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6142 ADS6142irhbt active vqfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6142 ADS6142irhbtg4 active vqfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6142 ads6143irhbr active vqfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6143 ads6143irhbt active vqfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6143 ads6144irhbr active vqfn rhb 32 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6144 ads6144irhbt active vqfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6144 ads6145irhbr active vqfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6145 ads6145irhbt active vqfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 az6145 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material)
package option addendum www.ti.com 10-jun-2014 addendum-page 2 (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of ADS6142 : note: qualified version definitions:
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ADS6142irhbr vqfn rhb 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ADS6142irhbt vqfn rhb 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ads6143irhbr vqfn rhb 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ads6143irhbt vqfn rhb 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ads6144irhbr vqfn rhb 32 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ads6144irhbt vqfn rhb 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ads6145irhbr vqfn rhb 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 ads6145irhbt vqfn rhb 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 package materials information www.ti.com 9-dec-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ADS6142irhbr vqfn rhb 32 3000 338.1 338.1 20.6 ADS6142irhbt vqfn rhb 32 250 210.0 185.0 35.0 ads6143irhbr vqfn rhb 32 3000 338.1 338.1 20.6 ads6143irhbt vqfn rhb 32 250 210.0 185.0 35.0 ads6144irhbr vqfn rhb 32 2500 338.1 338.1 20.6 ads6144irhbt vqfn rhb 32 250 210.0 185.0 35.0 ads6145irhbr vqfn rhb 32 3000 338.1 338.1 20.6 ads6145irhbt vqfn rhb 32 250 210.0 185.0 35.0 package materials information www.ti.com 9-dec-2013 pack materials-page 2

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